Electronic systems can typically include a data storage capability. For example, bi-stable circuits, such as flip-flops can maintain a data value in one of two binary logic values depending upon an input to the flip-flop. One commonly used bi-stable circuit that can maintain a logic value until another value is written or rewritten, is a latch.
A latch can take a number of different forms. For example, a latch can include cross-coupled inverters that can latch a data value on complementary data nodes until a new data value is rewritten. Such latches are often used as static random access memory (SRAM) cells. An SRAM type latch can store true and complementary logic values. Such stored data values can be read when, for example, an execution unit fetches data from an addressed storage cell.
Unlike memory cells that can require periodic refresh, an SRAM type latch can retain stored data without requiring refresh until such a time as power is removed from the latch. However, there are many applications in which it is desirable for a data value to be retained even in the absence of power. Thus, many conventional applications include both a volatile storage circuit and a nonvolatile storage circuit.
Typically, a volatile memory is situated within an integrated circuit that is separate from an integrated circuit including a nonvolatile memory. There may be instances, however, where both volatile and nonvolatile storage elements are included in the same integrated circuit. In such instances, data targeted for volatile storage elements can be generally altogether different from the data targeted for the volatile storage elements. For example, the different data sets may be for different applications.
However, in some applications, it may be desirable to utilize a storage device having both volatile and nonvolatile features for the same data value. For example, if data is to be temporarily held while power is present, a storage device can utilize a latch into which data can be written and thereafter read. However, if the data stored is of sufficient importance, the data could be maintained after power is removed by storing the data value into a nonvolatile storage element. Such a desired storage device could function essentially as a latch, but also include nonvolatile storage for latched data. Such a circuit can be considered a “programmable” latch.
Conventional programmable latches can utilize antifuse devices as nonvolatile storage elements. An antifuse device can have a first, relatively high impedance, in an unprogrammed state, and a second, relatively low impedance, in a programmed state. Due to process and other variations, the programming response for antifuse devices can vary. As a result, it is desirable to be able to test a state (e.g., impedance) of an antifuse device to ensure it has a low enough impedance after being programmed and/or a high enough impedance if not programmed.
Conventional antifuse based programmable latches and corresponding test arrangements will now be described with reference to FIGS. 7 and 8.
FIG. 7 shows a conventional programmable latch circuit 700 and corresponding test configuration. A conventional programmable latch circuit 700 can include an antifuse section 702, a load section 704, volatile latch 706, first test section 708, and second test section 710. One of the antifuse devices (AF1 or AF2) in antifuse section 702 can be programmed to establish a stored logic value. Such a value can be latched by volatile latch 706 by operation of load section 704. Ideally, a programmed antifuse device can draw a current greater than some minimum current, while an unprogrammed antifuse device can draw a current less than the minimum current (can be essentially zero).
As shown in FIG. 7, in a test operation, a power supply voltage vpwr can be applied to both the volatile latch circuit 706 and antifuse section 702. In addition, a test voltage vmrg can be applied to gates of transistors P70 and P71 to generate a test current Itest (not shown) when the circuit is closed by test control signals mrglb or mrgrb. According to test control signals mrglb and mrgrb, test current Itest can be applied to one latch node 712 or the other latch node 714. Ideally, a test current (Itest) can have a magnitude between that of an ideal programmed current value and an ideal unprogrammed current value.
More particularly, if antifuse device AF1 is being tested, second test section 710 can be enabled by signal mrgrb, while first test section 706 can be disabled by signal mrglb. If antifuse device AF1 is programmed properly, a current provided to node 712 by antifuse device AF1 will be greater than that provided to node 714 by test section 710. Volatile latch 706 can latch a data value according to a differential voltage between such nodes. In contrast, if antifuse device AF1 is not programmed properly, a current provided to node 712 can be less than that provided to node 714, and volatile latch 706 can latch an opposite data value. In the same fashion, if antifuse device AF2 is being tested, first test section 708 can be enabled by signal mrglb, while second test section 710 can be disabled by signal mrglb.
A conventional testing operation will now be described. In particular, in the testing of anti-fuse AF1, a sequencing of signals hldb, eq, ldb, and mrgrb can be used to evaluate a resistance of AF1. One such sequence would be to first set hldb voltage sufficiently high enough to turn off p-channel metal-oxide-semiconductor (PMOS) devices P72 and P73 within volatile latch 706. Second, signal eq can be driven to a voltage sufficiently high enough to turn on the n-channel MOS (NMOS) devices N70 and N71 within volatile latch 706, and remain high for a time sufficiently long enough to set the voltage at nodes 712 and 714 to a same or similar potential as vgnd.
Next, with eq still high, signals ldb and mrgrb can be driven to a voltage sufficiently low enough to enable load section 704 and to enable test PMOS device P74. Signal mrglb can remain at a voltage sufficiently high enough to disable the PMOS device P75 controlled by mrglb. Next signal eq would be set to a voltage sufficiently low to turn off NMOS devices N70 and N71. The circuit can remain in this state sufficiently long enough for current flowing through antifuse AF1 to charge up node 712 to a voltage Vtn high enough to turn on NMOS N72 of volatile latch 706, or for current flowing through second test circuit 710 to charge up node 714 to a voltage Vtn high enough to turn on NMOS device N73 in volatile latch 706. If node 712 reaches Vtn prior to node 714, then NMOS device N72 can turn on and discharge node 714 once again, reinforcing the state programmed into AF1 and showing that AF1 was of sufficiently low resistance. If node 714 reaches Vtn prior to node 712, then NMOS device N73 can turn on and discharge node 712 once again, reinforcing the test current, showing that AF1 was not of sufficiently low resistance.
A next step in this conventional sequence would be to set Idb and mrgrb to a voltage sufficiently high enough to turn off PMOS devices in load section 704 and PMOS device P74, Next, signal hldb can be set to a voltage low enough to enable PMOS devices P76 and P77 in volatile latch 706. This can hold the states of nodes 712 and 714 as determined in the prior steps. Finally, the signal out can be read by an external tester and compared to an expected state. If AF1 had a sufficiently low resistance, a low would be read on the out signal and the test would pass. Otherwise, a high would be read on the out signal and the test would fail.
A similar sequence can be executed for anti-fuse AF2, wherein a high on the out signal would indicate a passing test, while a low would indicate a failing test.
It is understood that both a power supply voltage (vpwr) and a test voltage (vmrg) are applied via external connections (e.g., from external test equipment). Thus, FIG. 7 shows a line 716 signifying a physical boundary of an integrated circuit containing the programmable latch.
A second conventional programmable latch circuit 800 and corresponding test arrangement is shown in FIG. 8. Conventional programmable latch circuit 800 can include antifuse section 802, load section 804, and a volatile latch 806. In addition, circuit 800 further includes first test section 808, and second test section 810.
In a test operation, a power supply voltage vpwr can be applied to volatile latch circuit 806 while a test voltage vpp can be applied to antifuse section 802. The programmed state of the anti-fuses can be loaded into the volatile latch through load section 804 by sequencing the ldb and hldb signals with a test voltage (vpp) applied. A test signal (test) can be asserted (driven high in this example). As a test voltage (vpp) is being applied, a current ipp can be measured at the vpp voltage source. If an antifuse device has been properly programmed, a current ipp will be greater than some minimum value.
The above conventional arrangements can have drawbacks however. In the conventional case of FIG. 7, in some test equipment, control of an applied test voltage (vmrg) may not be sufficiently precise to generate small enough test current values for acceptable test results. Thus, errors in such an applied test voltage can result in improper test results. In addition, because an applied test voltage (vmrg) can be referenced to external ground, such a test voltage can be subject to undue noise.
A drawback to the conventional arrangement of FIG. 8 is that such an approach can be slow. Because current measurement is performed by an applied voltage, a test is performed on one nonvolatile element at a time. Such added test time can translate into increased cost. Further, to ensure adequate accuracy in a current measurement, a tester may have to include a precision current sensing capability. This can require a more costly tester.
U.S. Patent Application filed on Jan. 30, 2006, having Ser. No. 11/343,341 titled ANTI-FUSE LATCH CIRCUIT AND METHOD INCLUDING SELF-TEST, by Stansell et al., now U.S. Pat. No. 7,339,848 issued on Mar. 4, 2008, discloses a programmable latch with self-test capabilities. The contents of this application are incorporated by reference herein.